In FIG. 1, a conventional master-slice type semiconductor integrated circuit device chip. Around an internal area 2 in which an internal integrated circuit is to be arranged, a first substrate area 3 of a first conductivity type divided into segments 3-1, . . . , 3-n and a second substrate area 4 of a second conductivity type divided into segments 4-1, . . . , 4-n are disposed. The respective substrate areas are connected by metallic wiring 5 to input/output pads 1.
FIG. 2 is an enlarged view of one cell constituting the input/output section within a broken line rectangle 6 in FIG. 1. In FIG. 2, as in FIG. 1, the cell includes an input/output pad 1, a first substrate segment 3-6 of the first conductivity type, a second substrate segment 4-6 of the second conductivity type, and metallic wiring 5.
FIG. 3 is a cross-sectional view of cell 6 of FIG. 1 or cell 6 through substrate segments 3-6 and 4-6 of FIG. 2. In FIG. 3, first substrate segment 3-6 of the first conductivity type and second substrate segment 4-6 of the second conductivity type are disposed in a semiconductor substrate 16. When first substrate segment 3-6 is of, for example, n-type, MOS diffusion regions 7 of the second conductivity type or p-type are formed in first substrate segment 1. MOS diffusion regions 8 of the first conductivity type or n-type are formed within p-type second substrate segment 4-6. There are further disposed a second conductivity type MOS gate 9 and a first conductivity type MOS gate 10. Thus, a first conductivity MOS transistor and a second conductivity type MOS transistor are formed. A first voltage supply terminal 11 to which a supply voltage of, for example, V.sub.DD, is applied is connected one of second conductivity type MOS diffusion regions 7 and also to a region 13 of first conductivity type. A second voltage supply terminal 12 at ground potential is connected to one of first conductivity type MOS diffusion regions 8 and also to a region 14 of the second conductivity type. A plurality of such second conductivity type MOS transistors are formed in one first conductivity type first substrate segment 3-6, and a plurality of such first conductivity type MOS transistors are formed in one second conductivity type second substrate segment 4-6.
In the conventional semiconductor integrated circuit device shown in FIG. 1, supply voltage V.sub.DD is applied to first conductivity type first substrate area 3, and ground potential is applied to second conductivity type second substrate area 4. In single cell 6 of FIG. 1 or the cell of the input/output circuit shown in FIG. 2, a plurality of second conductivity type MOS transistors in first substrate segment 3-6 and a plurality of first conductivity type MOS transistors in second substrate segment 4-6 are used to form inverter circuits to thereby provide an input/output circuit which couples input/output pad 1 and an integrated circuit formed within internal area 2.
As is well known, a master-slice LSI is processed in a master process until the step for forming transistors, and contact holes, metallic wiring layers, through-holes etc. are formed in the following slice process to complete an LSI. With respect to the arrangement shown in FIG. 2, a desired LSI is formed by arranging cells having the same slice processing data as those slice cells on the respective substrate segments on the master shown in FIG. 1.
In the above-described conventional master-slice semiconductor integrated circuit device, substrate areas 3 and 4 are both common to all the chips on the entire chip. Accordingly, if different supply voltages are used for one input/output circuit cell which are different from supply voltages used for another cell, current will flow through the respective substrate areas between the different voltage supply devices, which would disadvantageously cause generation of heat in tile substrate areas and increase in power consumption.
For example, Japanese Unexamined Patent Publication No. HEI 1-27332 discloses an LSI device which permits application of different supply voltages to a plurality of cells disposed on an integrated circuit chip. Separate wells are provided for a plurality of internal cells disposed within an internal cell area, and a plurality of voltage supply wires are disposed for applying different voltages to contact regions of the respective wells. Desired ones of such voltage supply wires are chosen for connection to desired wells. The invention disclosed in this Japanese Unexamined Patent Publication HEI 1-27332 is not directed to a cell structure which enables application of a plurality of supply voltages to input/output circuits which connect wells or substrate areas of internal cells to external circuits.
Japanese Unexamined Patent Publication No. HEI 1-257348 discloses an arrangement for preventing a voltage applied to small-current circuit cells arranged on a chip from being affected by other larger-current circuit cells on the same chip, a power supply circuit is provided in which substrate terminals for coupling a supply voltage to the chip substrate and voltage supply terminals each for coupling a supply voltage to the circuits in each cell are separately provided, and in order to connect the respective terminals to appropriate power supply pads for external connection are connected by either a first power supply wiring arrangement or a second power supply wiring arrangement. However, this publication does not mention at all an input/output circuit cell structure for applying a plurality of different supply voltages to input/output circuits. Further, there is no disclosure in this publication of selecting supply voltages for individual input/output circuit cells in the slice process.
Japanese Unexamined Patent Publication No. HEI 2-298066 discloses an arrangement in which a voltage supply circuit arrangement for a semiconductor integrated circuit device is divided into two parts, one for a group of Bi-MOS logic circuits and one for a group of CMOS logic circuits, for applying different supply voltages to the respective groups. However, there is no teaching as to how two supply voltages are externally applied or as to what structures input/output circuit cells have.